The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to a local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (xe2x80x9cDRAMxe2x80x9d).
Integrated circuit memory devices and those including embedded DRAM often use a local driver circuit to couple complementary data signals on a pair of global write data lines to a corresponding pair of local write data lines. Such conventional local drivers have utilized complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) pass (or transmission) gates comprising parallel coupled P-channel and N-channel transistors. These pass gates require activation by complementary write enable signals (WEN and WENB), with the former being used to activate the N-channel device while the WENB signal is used to activate the P-channel devices.
Disclosed herein is a local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal in order to couple complementary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.
Particularly disclosed herein is a local driver circuit for an integrated circuit memory array including complementary global write data lines and local write data lines. The driver circuit comprises a single write enable signal line for selectively coupling a data signal on a first one of the global write data lines to a first of the local write data lines and a complement to the data signal on a second of the global write data lines to a second of the local write data lines.
Also particularly disclosed herein is an integrated circuit device including a driver circuit for a memory array including complementary global write data lines and local write data lines. The driver circuit comprises first and second switching devices having a first terminal thereof respectively coupled to one of the complementary global write data lines and a control terminal thereof coupled to a write enable signal line. Third and fourth series connected switching devices are coupled between a supply voltage line and a reference voltage line, the third and fourth switching devices being coupled to one of the complementary local write data lines and the third and fourth switching devices including a control terminal thereof. Fifth and sixth series connected switching devices are also coupled between the supply voltage line and the reference voltage line, the fifth and sixth switching devices being coupled to another one of the complementary local write data lines and the fifth and sixth switching devices including a control terminal thereof. The control terminals of the third and sixth switching devices are coupled to a second terminal of the first switching device and the control terminals of the fourth and fifth switching devices are coupled to a second terminal of the second switching device. A seventh switching device is coupled between the complementary local write data lines and has a control terminal thereof coupled to the write enable signal line. Eighth and ninth switching devices couple the second terminal of the first switching device to the reference voltage line. The eighth switching device has a control terminal coupled to the second terminal of the second switching device and the ninth switching device has a control terminal coupled to the write enable signal line. Tenth and eleventh switching devices couple the second terminal of the second switching device to the reference voltage line. The tenth switching device has a control terminal coupled to the second terminal of the first switching device and the eleventh switching device has a control terminal coupled to the write enable signal line.